1. Field
Example embodiments relate to storage nodes, semiconductor memory devices, methods of manufacturing the storage nodes, and methods of manufacturing the semiconductor memory devices. Example embodiments also relate to storage nodes and phase change memory devices having an increased contact area between a bottom electrode contact layer and a phase change layer and methods of manufacturing the storage nodes and phase change memory devices.
2. Description of Related Art
Semiconductor memory devices typically include a switching device such as a transistor and a storage node electrically connected to the switching device. A phase change memory device is characterized by a phase change layer included in the storage node. A resistance of the phase change layer changes according to a state of the phase change layer (i.e., either a crystalline state or an amorphous state). Data can be recorded using this phenomenon by changing the phase change layer from the crystalline state to the amorphous state, or vice versa. Data can be read by measuring the resistance of the phase change layer.
For example, a phase change material may switch between a crystalline state and an amorphous state with changes in temperature. The crystalline or amorphous state of the phase change material may be reversible. Thus, the phase change material may change from the crystalline state to the amorphous state, or from the amorphous state to the crystalline state. The resistance of the phase change material in the crystalline state, for example, may be lower than the resistance of the phase change material in the amorphous state.
FIG. 1 is a cross-sectional view of a storage node of a conventional phase change memory device.
Referring to FIG. 1, a via hole 12 is formed in an insulating interlayer 10, and the via hole 12 is filled with a bottom electrode contact layer 14. The bottom electrode contact layer 14 is connected to a transistor (not shown) that is disposed under the storage node.
The bottom electrode contact layer 14 is formed using an electrode material layer to fill in the via hole 12 in the insulating interlayer 10 and then by planarizing a surface of the electrode material layer until a surface of the insulating interlayer 10 is exposed.
A phase change layer 16 covering the bottom electrode contact layer 14 is formed on the insulating interlayer 10. A top electrode 18 is formed on the phase change layer 16, and a top electrode contact layer 20 is formed on the top electrode 18.
In the above-described conventional phase change memory device illustrated in FIG. 1, when writing and reading are repeated, contact between the phase change layer 16 and the bottom electrode contact layer 14 may become poor because the phase change layer 16 and/or the bottom electrode contact layer 14 become exfoliated. Thus, the resistance of the phase change memory device increases and/or the current through the storage node is unstable, which makes it difficult to create state changes in the phase change layer. Accordingly, the writing and/or reading of information may become almost impossible.